Chapter — Microarchitecture (from assembly to pipelining)

1.RISC-V base — registers & instruction types

1.1Why we need a microarchitecture

RISC-V is an architecture (an ISA). A single-cycle CPU, a pipelined CPU, and a fancy out-of-order CPU can all implement that same ISA — they're different microarchitectures with different performance/cost trade-offs.

1.2The RISC-V register file

RV32I gives you 32 general-purpose registers, each 32 bits wide, named x0–x31. ABI names overlay them:

1.3Categories of instructions

Every RISC-V instruction falls into one of four behavioural categories:

1.4Six instruction formats

The 32-bit instruction word is sliced differently depending on what fields it needs. The category drives the format:

1.4.1Bit layouts

2.The single-cycle datapath

2.1The five universal tasks

Regardless of which instruction is executing, the hardware must (in order):

1. Fetch the instruction from instruction memory (IMEM) at address PC.
2. Decode it: pull the opcode, read up to 2 source registers, sign-extend the immediate.
3. Execute in the ALU: add, sub, compare, or compute an address.
4. Memory access (only for lw/sw): read or write data memory (DMEM).
5. Writeback: store the result into the destination register, and update PC.

2.2Datapath components

2.3Walkthrough — R-type (add x3, x1, x2)

1. PC drives IMEM → instruction fetched.
2. RegFile reads x1 and x2 in parallel.
3. ALU computes x1 + x2. DMEM is bypassed.
4. The ALU result is muxed into the RegFile's write port; on the next clock edge x3 ← result.
5. PC ← PC + 4.

2.4Walkthrough — lw x3, 12(x1)

1. Fetch the instruction.
2. RegFile reads x1; Imm Gen extracts 12.
3. ALU computes x1 + 12 = effective address.
4. DMEM reads the word at that address.
5. DMEM result → RegFile write port; x3 ← memory value on clock edge.

2.5Walkthrough — beq x1, x2, LABEL

1. Fetch + decode.
2. RegFile reads x1, x2. Imm Gen builds the branch offset.
3. ALU computes x1 − x2; zero-detect bit determines "taken".
4. A second adder (or the same ALU) computes PC + offset.
5. PC ← taken ? (PC + offset) : (PC + 4).

3.Single-cycle performance

3.1Performance definitions

To go faster, attack one of the three factors. Each microarchitecture style optimises a different one:

3.2The critical path

For single-cycle RISC-V, the critical path runs through lw (uses every block in series):

That's roughly the sum of five block delays. The whole machine is paying for the worst case every cycle — even for an add that doesn't touch DMEM. This is why single-cycle is slow.

3.3Worked example — single-cycle (Sarah Harris Ch. 7)

T_c   ≥ 250 + 150 + 200 + 250 = 850 ps  (round to typical 750-1000 ps in textbooks)
CPI   = 1
For 100 billion instructions:
  Time = 10^11 × 1 × 750 ps = 75 seconds

4.From single-cycle to multicycle

4.1The motivation — why split the cycle

In single-cycle, an add uses IMEM + RF + ALU + RF write (~600 ps) but the clock is sized for lw (~850 ps). The add wastes ~250 ps of every clock doing nothing.

4.2The multicycle datapath

Same blocks as single-cycle (PC, IMEM, RegFile, ALU, DMEM), but now one block is active per clock. Between clocks, an internal register holds intermediate values (the ALU output, the fetched instruction, the memory data, etc.).

4.3Per-instruction state count

Not every instruction needs all 5 states — that's the whole point. The control unit is a small FSM that walks through only the states each instruction needs:

4.4Performance — CPI rises, T_c falls

4.4.1Worked example

CPI_multi = 0.25·5 + 0.10·4 + 0.13·3 + 0.52·4
          = 1.25 + 0.40 + 0.39 + 2.08
          = 4.12

Time_multi = 10^11 × 4.12 × 250 ps = 103 seconds

4.5Did we win or lose?

5.The pipelined datapath

5.1The five stages

These map 1-to-1 onto the five universal tasks from §2.1.

5.2Pipeline registers

Between every pair of stages we drop a clocked register: IF/ID, ID/EX, EX/MEM, MEM/WB. They carry forward whatever state the next stage needs (rs values, immediate, control signals, the destination register number, the ALU result, etc.).

5.3Steady-state throughput & speedup

• Startup fill: first instruction finishes at cycle 5 (one full trip through the pipe).
• Steady state: from cycle 5 onward, one instruction completes every cycle ⇒ ideal CPI = 1.
• T_c: dictated by the slowest single stage, not the sum. Roughly 5× shorter than single-cycle.

6.Pipeline hazards

6.1Data hazards — RAW, WAR, WAW

WAR and WAW only matter in out-of-order pipelines (see Advanced µArch). RAW is the one we deal with in the 5-stage in-order pipe.

6.2Forwarding (bypassing)

Most RAW hazards can be solved without stalling. The ALU result is already computed at the end of EX — feed it directly to the next instruction's ALU input, instead of waiting for it to land in the RegFile two cycles later.

• EX/MEM → EX forward: previous instruction's ALU result → current instruction's ALU input.
• MEM/WB → EX forward: instruction-two-ahead's result.

6.3The load-use hazard (one unavoidable stall)

6.4Control hazards — branch flushes

A branch resolves in EX. By that point, two instructions are already in IF and ID. If the branch is taken (or mispredicted), both must be flushed (turned into NOPs) and the correct path re-fetched.

Branch prediction (covered in Advanced µArch) is how we get P(correct) close to 100%.

6.5Structural hazards

Two stages want the same hardware in the same cycle. The classic example: IF and MEM both touching memory.

• Fix: split caches — separate I-cache (for IF) and D-cache (for MEM). RISC-V CPUs do this by convention.
• Other fix: duplicate the unit, or stall one stage.

7.Pipelined performance math

7.1Per-type CPI

7.2Weighted-average CPI

The recipe:

1. For each instruction type, find its share of the program (e.g. 25% loads).
2. For each type, compute its CPI: P(no stall)·1 + P(stall)·stallCost.
3. Sum the products. Done.

7.3SPECINT2000 worked example

CPI_avg = 0.25·1.4 + 0.10·1.0 + 0.13·2.0 + 0.52·1.0
        = 0.35 + 0.10 + 0.26 + 0.52
        = 1.23

7.4Speedup recap

Time_pipelined = 10^11 × 1.23 × 350 ps = 43 seconds

Next: Advanced µArch → (branch prediction, superscalar, OoO + renaming)