CAAL Finals — Visual Exam Prep

Computer Architecture & Assembly Language · revision pack with diagrams, formulas, numeric examples, and pointers back into the source PDFs.

RISC-V Pipelining Superscalar / OoO Cache & VM Vector (RVV) Green Computing UVM / DV

⬇️ Download CAAL Notes (ZIP, ~65 MB) 🎯 Take the Quiz 🃏 Flashcards All PDFs · GQ images · pre-MT material · source PowerPoints

Exam composition

Sir's reported breakdown — no descriptive questions, MCQs only. Grand Quiz problems are fair game.

40% Pre-MT

Topic	MCQs
Pipelining (SC, perf, hazards)	5
Vector / RVV assembly	5

60% Post-MT

Topic	MCQs
Advanced µArch (deeper pipes, μops, BP, SS, OoO+renaming)	10
Memory Systems (cache, VM, perf)	20
Green Computing	5
Design Verification	5

Heads up Memory (20 MCQs) is the heaviest single block. Cache + VM + AMAT math should be muscle memory by exam day.

The one formula that ties it all together

Big idea Cumulative Performance = CPU Performance + Memory Performance
↳ You can't speed up real programs without taming the memory hierarchy. Even a great pipeline stalls if AMAT is high.

Performance cheatsheet

CPU side

Execution Time = #Inst × CPI × T_c
CPI            = Σ (fraction_i × CPI_i)
Speedup        = T_old / T_new

Pipelined ideal CPI = 1. Hazards (RAW, control, structural) push it up.

Memory side

AMAT = t_hit + MissRate × MissPenalty

3-level (cache → MM → VM, no TLB):
AMAT = t_cache
     + MR_cache × (t_MM + MR_MM × t_VM)

With TLB + multi-level page table:
AMAT = t_TLB + MR_TLB × (n × t_pagewalk)
     + (t_cache + MR_cache × (t_MM + MR_MM × t_VM))

Amdahl-style cache speedup

MSCPI_ideal = CPI_base
MSCPI       = CPI_base + f × MR × Penalty

Speedup = MSCPI / MSCPI_ideal
        = (CPI_base + f·MR·Penalty) / CPI_base

f = fraction of memory instructions (loads + stores).

Cache address split

Block offset bits = log2(b)   ; b = words/block × bytes/word
Set index bits    = log2(S)   ; S = #sets = C / (N × b)
Tag bits          = addr_bits − idx − off

N = associativity. Direct-mapped ⇒ N = 1.

Learning path — read in this order

Each chapter builds directly on the previous one. The story is: assembly → single-cycle → multicycle → pipelined → superscalar → OoO → memory → combined system.

1 · 📐 Microarchitecture

The foundation chapter. RISC-V base → instruction formats (R/I/S/B/U/J) → single-cycle datapath → critical path & CPI → multicycle → pipelined → hazards → pipelined CPI math.

~5 MCQs · the longest chapter

2 · 🚀 Advanced µArch

Continues from the pipelined CPU. Deeper pipes, µops, branch prediction (1-bit/2-bit FSMs), in-order superscalar, OoO + register renaming + new stages, ROB.

~10 MCQs

3 · 🧠 Memory Systems

The other half of CPU performance. Hierarchy & locality → caches (DM/assoc) → AMAT → virtual memory → page tables → multi-level PT → TLB → memory-stall CPI.

~20 MCQs — heaviest block

4 · ⚙️ System Performance

The unifying chapter. Combines pipeline CPI + AMAT into the full effective CPI, IPC, and execution time. End-to-end worked example.

Glues everything together

5 · 🔢 Vector / RVV

Data-level parallelism. VLEN, SEW, LMUL, AVL/VLMAX/VL, vsetvli, strip-mining loops. Why RVV beats SSE/AVX.

~5 MCQs

6 · 🌱 Green Computing + DV

Power vs energy, Dennard scaling, dark silicon, PUE, carbon intensity; UVM testbench anatomy.

~10 MCQs (5 + 5)

🎯 Quiz

25 interactive MCQs across all topics. Live score, click-to-reveal feedback.

🃏 Flashcards

50+ flip cards. Mark known/unknown, shuffle, filter by deck.

🧮 Worked Grand Quiz Examples

Step-by-step walkthroughs of GQ problems — branch mispredictions, ROB stalls, multi-level PT sizing, AMAT, cache config.

Source material map

Where to dig deeper Every page links back to specific PDFs & pages. Quick map:

Topic	File	Chapter / Pages
Single-cycle, pipelined, hazards	`RiscV_Sarah_Harris.pdf`	Ch. 7 (also `Microarchitecture/Ch7_MicroArch.pdf`)
Branch prediction	`Microarchitecture/Branch Prediction.pptx.pdf`	1-bit, 2-bit FSMs + worked CPI
Advanced µArch (SS / OoO / renaming)	`Microarchitecture/Advanced_Microarchitecture_Notes.pdf`	§1-5 (front-end → exec engine → back-end)
Memory hierarchy & cache	`Memory Systems/Ch8_Memory.pdf`, `MemorySystems.pdf`	Ch. 8 — Figures 8.23 (PT), 8.27 (multi-level)
Vector / RVV	`Vector Processing/Vector_concise.pdf`	Programming model, vsetvli, worked example
Green Computing	`Green Computing/GreenComputing.pdf`, `Circuit_Cloud_Carbon.pdf`	Power wall, DSAs, PUE, carbon
Design Verification	`DesignVerification/Demo Session.pdf`, `Talk_On_Verification.pdf`	UVM testbench components
Grand Quiz problems	`GQ/*.jpeg`	Past quiz handwritten work